
DS3106
18
7.6
Input Clock Priority and Switching
The SRCSW input pin controls reference switching between two clock inputs. In this mode, if the SRCSW pin is
high, the T0 DPLL is forced to lock to input IC3. If the SRCSW pin is low the device is forced to lock to input IC4.
The currently selected reference is indicated in the
PTAB1:SELREF field.